代做 EE1636、代写 java/Python 编程

日期：2025-05-24 09:37

DEPARTMENT OF ELECTRONIC & ELECTRICAL ENGINEERING

Pro-forma to accompany assignment/coursework 2023/2024

This pro-forma should be the first page to any set assignment/coursework. A full assignment brief should accompany this pro-forma.

Module Code: EE1636 Module Leader:

Module Title: Digital Logic Techniques Assessment Title: Digital

Weighting: 25%

Main objectives of the assessment: To enable the student to demonstrate their understanding of Number Systems , Detect and correct an error, Combinational Logic System and Sequential Logic system

Brief Description of the assessment: Truth table, the 1st canonical form, the 2nd canonical form equation and Karnaugh maps are essential concepts in combinational logic system. Sequential principles, TFFs (synchronous and asynchronous), JKFF, DFF, State Transition Diagram, and Present/Next state table are essential concepts in the sequential logic system. With a clear understanding of nature of those components. The student will employ corresponding knowledge to generate a combinational logic system-based solution or a sequential logic system based solution for a simple practical problem.

      Learning outcomes for the assessment:

A) NumberSystems

Understanding of the differences between analogue and digital signal processing, digital data formats and the need for them

B) Combinational Logic System

Understand of fundamental concept on truth table, the 1st canonical form, the 2nd canonical form equation and Karnaugh maps, Be able to solve problem by using the above concepts

C) Sequential Logic System

Understand of fundamental concept on Sequential principles, TFFs (synchronous and asynchronous), JKFF, DFF, General form of a sequential circuit; synchronous binary and non-binary counters; synchronous sequential design; cellular logic; autonomous sequential circuits; state transition diagrams; state minimization and be able to solve the problem by using the above concepts

D) Beabletodrawthecircuitdiagramwith the result generated with the above concepts

Assessment and marking criteria The students will be required to:

• Conversion between binary and decimal, Conversion between BCD and decimal, Conversion between base n and decimal; Detect and correct error with parity block check scheme; (20%)

• Demonstrate the understanding on truth table; Demonstrate the understanding on the 1st canonical form and the 2nd canonical form; Demonstrate the understanding on Karnaugh maps; Demonstrate the understanding on the assignment of logic level, the minimal NAND and NOR, and the circuit; (30%)

• Demonstrate the understanding of Sequential principles; Demonstrate the understanding of the JKFF; Demonstrate the understanding of the TFFs; Demonstrate the understanding of the DFF; (30%)

• Draw the circuit and Report Writing (20%)

Assessment method by which a student can demonstrate learning outcomes:

Written report

Format for the assessment/coursework (Guidelines on the expected format and length of submission):

Not more than 20 pages of A4 including figures/tables.

Distribution date to students: 7th May 2025 Submission Deadline: 11:50 pm 31st May 2025

Indicative Reading List:

All the information you should need is contained in the assignment brief.

Further information:

Please reserve ENOUGH time to submit your report.

TWO HOURS earlier submission attempt is highly recommended.

A)Number Systems

The data for this assignment is to be derived from your own Brunel student number. The number 2279803 will be used as an example as to how you should derive your numbers and examples are given in brackets for this number. You should however use YOUR OWN NUMBER. If you do not then you will be awarded zero marks. The majority of the marks will be awarded for the methods you are using so show all steps in your calculations. An answer to any question, which just gives a numerical solution without any explanation as to how it has been derived will receive zero marks even if it is the correct answer.

NOTE:

In order to create an appropriate number for calculation,

If the last TWO digits of your new format student number are zero or very small (less than 05) please further REVERSE the sequence of the last FOUR digits of your new format student number (245ABCD to 245DCBA). If not, please skip this step.

For example,

Student number 2458803: it is reversed to 2453088 Student number 2458853: NO REVERSE is needed

After the above preparation work, “your number” for the following questions is generated.

1. a) Take the 4 least significant digits of your number (Example 3089) and convert it to binary. Check your answer by converting it back to decimal. Show all steps of your working.

b) Take your binary number calculated in question 1 a) and convert it to i. Hexadecimal

ii. Base 12

Check each answer by converting it back to decimal and compare with the last four digits of your student number. Show all steps of your working.

2. Take the 4 least significant digits of your number and insert a decimal point to give two integer digits and two fractional digits (Example 30.89). Convert your number to binary with the fractional part accurate to 4 bits. Check your answer by converting it back to decimal. Show all steps of your working.

3. Using the whole of your student number (2459xxx), convert it to:

i. 8421 BCD

ii. 74-2-1 BCD

4. Take the 2 least significant digits of your student number (Example 77). If the number >65, subtract 20. If 65 > the number > 32, use the number without any subtraction. If the number <33 (as in the example) then add 20. Eventually you will get your reference number. Obtain a table of ALL Gray coded numbers from your reference number up to your reference number + 15 (for example, if your reference number is 15, then provide the a table of Gray coded number from 15 to 15+15=30 ) and hence obtain the Gray code of this 16 numbers.

5. Take the 8421 BCD answer from question 3, and arrange the data as a block of seven 4-bit words. Apply a parity block check coding of your choice (odd or even parity). Pretend that the data has been transmitted to another digital system and in the process ONE bit of the data field has been corrupted. (i.e. invert one bit of the data). Show how the parity block check scheme can DETECT and CORRECT the error.

If TWO errors are introduced into the data show that the errors CAN be detected but CANNOT be corrected.

B) Combinational Logic System

Your logic function for this assignment is to be derived from your own birthday. Add your date of birth, using 2 digits for the day (DD), 2 for the month (MM) and the last 2 digits of the year (YY). Then convert it to 3 BASED number and take the last digit 1 (the LSB). Select one of the following functions

(𝐹 to 𝐹 ) with the number you have obtained (the LSB). 02

𝐹 = f(ABCD) = ∑(0, 2, 4, 5, 10, 11, 13, 15) 0

𝐹 = f(ABCD) = ∑(2, 3, 5, 7, 8, 10, 12, 13) 1

𝐹 = f(ABCD) = ∑(0, 2, 3, 5, 7, 9, 12, 13) 2

For example, if your birthday is 23rd January 2005, then the number you should use is

230105(DDMMYY), giving you DD+MM+YY=23+01+05=29. Then convert it to 3 BASED number

1002 and take the last digit 2 (the LSB). Therefore, the 𝐹 is selected as your own personal function. 32

You should however use YOUR OWN FUNCTION. If you do not then you will be awarded zero marks.

1 Write down the shorthand 1st canonical form equation of your own personal function derived as above. Obtain the full 1st canonical form Boolean equation of your function in AND/OR/NOT form and draw its gate-level circuit diagram. Obtain the shorthand equation of the 2nd canonical form of your function. Obtain the full 2nd canonical form Boolean equation of your function in AND/OR/NOT form and draw its gate-level circuit diagram. Enter your function into a fully labelled K-Map.

2 Obtain the minimal 1st canonical form equation (AND/OR/NOT) of your function and draw its circuit diagram. Obtain the minimal 2nd canonical form equation (AND/OR/NOT) of your function and draw its circuit diagram. Use truth table equivalence to show that your minimal 1st and 2nd canonical form equations do perform the same function.

3 Obtain the minimal NAND version of your function and draw its circuit diagram; Obtain the minimal NOR version of your function and draw its circuit diagram.

4 Select at random, 4 terms NOT included in your original 1st canonical form shorthand equation in Question 1, to be don’t care states. Obtain the minimal 1st canonical form (AND/OR/NOT) using the original terms and, where appropriate, the don’t care conditions. Draw the circuit diagram; Obtain the minimal 2nd canonical form (AND/OR/NOT) using the original terms and where appropriate, the don’t care conditions. Draw the circuit diagram.

5 Provide discussion on timing hazard concept with the circuits in question 4. If necessary modify the circuits to remove them by using appropriate redundant terms, giving the Boolean equations for the hazard-free circuits. If no hazard is found, give your explanation with a hazard example.

C) Sequential Logic System

Your logic function for this assignment is to be derived from your own birthday. Add your date of birth, using 2 digits for the day (DD), 2 for the month (MM) and the last 2 digits of the year (YY). Select one of the number Set (EVEN,ODD) with the digit you have obtained (EVEN or ODD)

0,1,5,3,7,6,2,4 ---- EVEN 0,6,2,4,5,1,7,3 ---- ODD

For example, if your birthday is 23rd Jan 2005, then the number you should use is 230105, giving you 23+01+05=29. Therefore, the second number set (ODD) {0,6,2,4,5,1,7,3} is selected as your number set.

1. Design a sequential system to continuously output your set of eight different digits in binary at the rate of one digit per clock pulse. In this design, for the next state logic sub-system, you should use a 3-bit asynchronous counter with the clock as the data input. Obtain any other necessary logic functions in their minimal 1st Canonical AND/OR/NOT form, and obtain their Boolean equations. Draw a gate-level circuit diagram of your system.

NOTE. Use the appropriate symbol for each flip-flop used. You do NOT need to show the circuit diagram within the flip-flops. This applies to all circuit diagrams in this assignment.

Identify ONE change of state in the asynchronous counter that creates a timing problem on the output and identifies the resulting instantaneous erroneous outputs.

2. Redesign your system in question 1 using

i. An eight-state next-state logic system designed using synchronous trigger

flip-flops where the state sequence is in ascending pure binary code, and an appropriate Output Logic Encoder is used.

Redesign your system in question 1 using

ii. A next-state logic system designed using synchronous trigger flip-flops where the state sequence is your set of numbers and NO OUTPUT LOGIC is required.

NOTE. No external input is required in either of these designs.

Present minimal 1st canonical form AND/OR/NOT Boolean equations of any combinational logic used and give circuit diagrams of your systems.

Compare and contrast your designs in questions 1 and 2 in terms of the amount of hardware required and ease of design. Comment on any likelihood (on not) of timing problems with Question 2 designs.

3. Take your number set and remove the ‘0’ from the first digit and the last digit. Then repeat the red digit in the middle to generate your new number set A which contains 7 digits. Take the number set (EVEN) for example,

0,1,5,3,7,6,2,4 --- we get 1,5,3,7,6, 2 --- we get 1,5,3,7,7, 6,2 ---

remove ‘0’ and last digit, repeat the red digit in middle, this is your new number set A.

Design a sequential system to continuously output your new number set A at the rate of one digit per clock pulse. Your next state subsystem should be a SEVEN-state machine based on JK flip-flops. The driving functions and any other necessary logic should be in minimal 2nd Canonical AND/OR/NOT form, and presented as Boolean equations.

Draw a detailed logic diagram of your system.

How would you modify your system so that the sequence stops at the end of your new number set A, after having output all the digits once? Identify any changes to the flip-flop driving functions needed to achieve this.

4. Design a sequential system that has an input variable I. When I=1 the system should output continuously your new number set obtained in question 3 in binary. If however I is set to 0 at any time your system must output your number set in reverse order, starting at the digit reached at the instant I was set to 0. Subsequent changes to the input I must cause the digits to be output in forwarding order (I=1) or reverse order (I=0). On reaching the end of the number with I=1, start outputting the number set again from the first digit. On reaching the beginning of the number with I=0 start outputting the number again from the last digit.

Use Data/delay flip-flops in your design and obtain any necessary combinational logic in its minimal NAND form, giving the appropriate Boolean equations.

Draw a detailed logic diagram of your system.

5. Take your number set and remove the ‘0’ from the first digit and the last two digits to generate your new number set which contains 5 digits. From this number set obtain a 5- bit binary number by replacing the odd digits by 1 and the even digits by 0.

Take the number set (EVEN) for example,

0,1,5,3,7,6,2,4 --- remove ‘0’ and last two digits,

we get 1,5,3,7,6 --- this is your new number set B,

then replace odd digits by 1 and even digits by 0

we get 11110 --- this is your 5-bit binary number.

You are now required to design a sequence detector which will indicate each time your 5- bit number has occurred in a stream of random bit-serial data. The detection of your number is indicated by setting an output variable, Z, to 1.

Obtain a State Transition Diagram for your system and from this diagram determine the sequence of state transitions for a random stream of 20 bits of data of your choice, which includes at least one occurrence of your five-bit number.

Obtain the Present/ Next State table of your system and if possible, state minimise the system.

Design the system using Delay/data flip-flops. Obtain any necessary combinational logic in its minimal NOR form, giving the appropriate Boolean equations.

Draw a detailed logic circuit of your system.

Please give an accurate estimate of the time (in hours) spent on this assignment.